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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:46:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:46:35 -0700 |
| commit | a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91 (patch) | |
| tree | 49e471ade09346f2c17ebd00205e3dc70d1f7691 /passes/techmap/abc9.cc | |
| parent | 6d74b3e004455a98d785bd27c4276b787af637a7 (diff) | |
| download | yosys-a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91.tar.gz yosys-a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91.tar.bz2 yosys-a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91.zip | |
Fix initialisation of flops
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4bb4058b1..51bea4d57 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -520,8 +520,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri continue; } else if (cell->type.in("$_FF_")) { - SigBit D = cell->getPort("\\D"); - SigBit Q = cell->getPort("\\Q"); + RTLIL::Wire *D = cell->getPort("\\D").as_wire(); + RTLIL::Wire *Q = cell->getPort("\\Q").as_wire(); + Q->attributes.swap(D->attributes); module->connect(Q, D); it = module->cells_.erase(it); continue; |