diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:12:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:12:38 -0700 |
| commit | 71649969213863b2695f1c51956886fc7879c3e6 (patch) | |
| tree | 7fb2cf4be9d2d5628dc4c54a8c9161fd57e62bfd /passes/techmap/abc9.cc | |
| parent | e6d5147214bd157c457654dc46547775ec6ad324 (diff) | |
| download | yosys-71649969213863b2695f1c51956886fc7879c3e6.tar.gz yosys-71649969213863b2695f1c51956886fc7879c3e6.tar.bz2 yosys-71649969213863b2695f1c51956886fc7879c3e6.zip | |
RTLIL::S{0,1} -> State::S{0,1}
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 34919cf07..31c1d6f80 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -593,7 +593,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri c->setPort("\\Y", module->addWire(NEW_ID)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); log_assert(wire); - module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); + module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); } else if (!lut_costs.empty() || !lut_file.empty()) { RTLIL::Cell* driver_lut = nullptr; |