diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 12:55:47 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 12:55:47 -0800 |
| commit | 51f28a67473f503d310b9add2d7a68fc8523faff (patch) | |
| tree | cdbad0b27fa48128d39ef28417bdec4e94e16823 /passes/techmap/abc9.cc | |
| parent | d56f02d1fc1d0482aa57b07f24213f5e0c16faea (diff) | |
| download | yosys-51f28a67473f503d310b9add2d7a68fc8523faff.tar.gz yosys-51f28a67473f503d310b9add2d7a68fc8523faff.tar.bz2 yosys-51f28a67473f503d310b9add2d7a68fc8523faff.zip | |
abc9 to call "clean" once at the end of all abc9_module() calls
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ce93d3fe0..f6ace6a94 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -409,6 +409,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str())); + design->selection_stack.pop_back(); + // Now 'unexpose' those wires by undoing // the expose operation -- remove them from PO/PI // and re-connecting them back together @@ -919,8 +921,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // log("Don't call ABC as there is nothing to map.\n"); //} - Pass::call(design, "clean"); - cleanup: if (cleanup) { @@ -928,8 +928,6 @@ cleanup: remove_directory(tempdir_name); } - design->selection_stack.pop_back(); - log_pop(); } @@ -1540,6 +1538,8 @@ struct Abc9Pass : public Pass { } } + Pass::call(design, "clean"); + assign_map.clear(); signal_map.clear(); signal_init.clear(); |