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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:28:30 -0700 |
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committer | GitHub <noreply@github.com> | 2019-06-14 10:28:30 -0700 |
commit | 474fe9f47ae9c8a022d726a1b674853ca3236db0 (patch) | |
tree | 91907bc7387e194d64d5503dec4bf4c7987593ae /passes/techmap/abc9.cc | |
parent | bc22e2e3ee120aeb84323ce52031b895f9f62f54 (diff) | |
parent | 95665730540c0fd7c76690f28d0fd6b5f13f2223 (diff) | |
download | yosys-474fe9f47ae9c8a022d726a1b674853ca3236db0.tar.gz yosys-474fe9f47ae9c8a022d726a1b674853ca3236db0.tar.bz2 yosys-474fe9f47ae9c8a022d726a1b674853ca3236db0.zip |
Merge pull request #1097 from YosysHQ/dave/xaig_ecp5
Add ECP5 ABC9 support (to xaig branch)
Diffstat (limited to 'passes/techmap/abc9.cc')
-rw-r--r-- | passes/techmap/abc9.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index a6ec4a6fb..d4f5c5238 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -22,7 +22,16 @@ // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification // http://www.eecs.berkeley.edu/~alanmi/abc/ +#if 0 +// Based on &flow3 - better QoR but more experimental +#define ABC_COMMAND_LUT "&st; &ps -l; "/*"&sweep -v;"*/" &scorr; " \ + "&st; &if {W}; &save; &st; &syn2; &if {W}; &save; &load; "\ + "&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\ + "&st; &if -g -K 6; &synch2; &if {W}; &save; &load" +#else #define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; "*/"&retime; &dch -f; &ps -l; &if {W} -v; "/*"&mfs; "*/"&ps -l" +#endif + #define ABC_FAST_COMMAND_LUT "&st; &retime; &if {W}" |