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authorEddie Hung <eddie@fpgeh.com>2019-06-14 13:07:56 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-14 13:07:56 -0700
commit2d85725604271c658382e8fdd8ff28275fb94b03 (patch)
treee20bd94404cc1d4992cd662207ffe7edd4c96690 /passes/techmap/abc9.cc
parent8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (diff)
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Get rid of compiler warnings
Diffstat (limited to 'passes/techmap/abc9.cc')
-rw-r--r--passes/techmap/abc9.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fe199f886..f7f2e862a 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -243,8 +243,8 @@ struct abc_output_filter
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
- bool keepff, std::string delay_target, std::string lutin_shared, bool fast_mode,
- const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file,
+ bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
+ bool show_tempdir, std::string box_file, std::string lut_file,
std::string wire_delay)
{
module = current_module;
@@ -835,7 +835,7 @@ struct Abc9Pass : public Pass {
std::string script_file, clk_str, box_file, lut_file;
std::string delay_target, lutin_shared = "-S 1", wire_delay;
bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
- bool show_tempdir = false, sop_mode = false;
+ bool show_tempdir = false;
vector<int> lut_costs;
markgroups = false;
@@ -997,7 +997,7 @@ struct Abc9Pass : public Pass {
if (!dff_mode || !clk_str.empty()) {
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
- delay_target, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode,
+ delay_target, lutin_shared, fast_mode, show_tempdir,
box_file, lut_file, wire_delay);
continue;
}
@@ -1143,7 +1143,7 @@ struct Abc9Pass : public Pass {
en_polarity = std::get<2>(it.first);
en_sig = assign_map(std::get<3>(it.first));
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
- keepff, delay_target, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode,
+ keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
box_file, lut_file, wire_delay);
assign_map.set(mod);
}