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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-11 23:25:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-13 13:29:03 +0200 |
| commit | 0c5db07cd6cc3c19b926da21a46599f97592b20f (patch) | |
| tree | 7f9e731067e7bc75524837b04ab245e3300ee18b /passes/techmap/abc9.cc | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-0c5db07cd6cc3c19b926da21a46599f97592b20f.tar.gz yosys-0c5db07cd6cc3c19b926da21a46599f97592b20f.tar.bz2 yosys-0c5db07cd6cc3c19b926da21a46599f97592b20f.zip | |
Fix various NDEBUG compiler warnings, closes #1255
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7418ed4a3..da376d09e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -741,7 +741,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto driver_cell : bit_drivers.at(it.first)) for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); - bool no_loops = toposort.sort(); + bool no_loops YS_ATTRIBUTE(unused) = toposort.sort(); log_assert(no_loops); for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) { |