Merge remote-tracking branch 'upstream/master'

1 files changed, 3 insertions, 3 deletions

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 5b19d84fb..65c7d1bb8 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 					continue;
 				}
 			}
-
-			cell_stats[RTLIL::unescape_id(c->type)]++;
+			else
+				cell_stats[RTLIL::unescape_id(c->type)]++;
 
 			if (c->type == "\\_const0_" || c->type == "\\_const1_") {
 				RTLIL::SigSig conn;
@@ -1453,7 +1453,7 @@ struct AbcPass : public Pass {
 		log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
 		log("ABC on logic snippets extracted from your design. You will not get any useful\n");
 		log("output when passing an ABC script that writes a file. Instead write your full\n");
-		log("design as BLIF file with write_blif and the load that into ABC externally if\n");
+		log("design as BLIF file with write_blif and then load that into ABC externally if\n");
 		log("you want to use ABC to convert your design into another format.\n");
 		log("\n");
 		log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");