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| author | Aman Goel <amangoel@umich.edu> | 2018-08-18 08:18:40 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-18 08:18:40 +0530 |
| commit | 61f002c908830d59e883d25668b731e7d12470d0 (patch) | |
| tree | 25174f7321f60e14ca6c144544f29971c40abe9b /passes/techmap/abc.cc | |
| parent | 5dcb899e76a82c8aa84552a59f4a9f64394e7785 (diff) | |
| parent | e343f3e6d475984c21611474bffe7dcd8f599497 (diff) | |
| download | yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.gz yosys-61f002c908830d59e883d25668b731e7d12470d0.tar.bz2 yosys-61f002c908830d59e883d25668b731e7d12470d0.zip | |
Merge pull request #3 from YosysHQ/master
Updates from official repo
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 18868c6d7..d2d15a4a9 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1248,7 +1248,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin struct AbcPass : public Pass { AbcPass() : Pass("abc", "use ABC for technology mapping") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1420,7 +1420,7 @@ struct AbcPass : public Pass { log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ABC pass (technology mapping using ABC).\n"); log_push(); |