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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 16:30:17 -0700 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 16:30:17 -0700 |
commit | 4afcad70e264d58bcbb8cddcffd19673c3570fc6 (patch) | |
tree | addfda1969a4ad443b1c763420c2fb5171858e39 /passes/techmap/abc.cc | |
parent | a5f33b5409d9325730204eb776e0046726d55d2c (diff) | |
parent | ad602438b8313c3dd243c5fabf6f20036487d1ba (diff) | |
download | yosys-4afcad70e264d58bcbb8cddcffd19673c3570fc6.tar.gz yosys-4afcad70e264d58bcbb8cddcffd19673c3570fc6.tar.bz2 yosys-4afcad70e264d58bcbb8cddcffd19673c3570fc6.zip |
Merge branch 'eddie/fix_retime' into xc7srl
Diffstat (limited to 'passes/techmap/abc.cc')
-rw-r--r-- | passes/techmap/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 4876f3009..e2a152348 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1728,7 +1728,7 @@ struct AbcPass : public Pass { signal_init[initsig[i]] = State::S0; break; case State::S1: - signal_init[initsig[i]] = State::S0; + signal_init[initsig[i]] = State::S1; break; default: break; |