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author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 08:40:31 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:49:43 +0200 |
commit | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (patch) | |
tree | ed08831d07df4e799d881349c36acf76bf277791 /passes/sat/share.cc | |
parent | 260c19ec5a3adb292158658dd69a352b9325ab64 (diff) | |
download | yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.tar.gz yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.tar.bz2 yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.zip |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Diffstat (limited to 'passes/sat/share.cc')
-rw-r--r-- | passes/sat/share.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 724bc3f98..c209e8ed7 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.size(), 0); - RTLIL::SigSpec new_y2(y, y2.size(), 0); + RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); + RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.size(), 0); - RTLIL::SigSpec new_y2(y, y2.size(), 0); + RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); + RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -620,7 +620,7 @@ struct ShareWorker RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1)); } if (all_cases_wire->width == 1) return all_cases_wire; |