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| author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
| commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
| tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /passes/sat/expose.cc | |
| parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
| parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
| download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip | |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'passes/sat/expose.cc')
| -rw-r--r-- | passes/sat/expose.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 80ab82cd5..5fe7efc34 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -217,7 +217,7 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width struct ExposePass : public Pass { ExposePass() : Pass("expose", "convert internal signals to module ports") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -254,7 +254,7 @@ struct ExposePass : public Pass { log(" designator for the exposed signal.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { bool flag_shared = false; bool flag_evert = false; |