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author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:15:14 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
commit | 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch) | |
tree | 27801c4b0171a2491ff6817ebb6d2a1d1484c086 /passes/sat/expose.cc | |
parent | 16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff) | |
download | yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.gz yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.bz2 yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.zip |
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'passes/sat/expose.cc')
-rw-r--r-- | passes/sat/expose.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 4308e7364..c9363f4bf 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -649,7 +649,7 @@ struct ExposePass : public Pass { { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); - w->width = it.second.__width; + w->width = it.second.size(); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) |