diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-06-08 15:12:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-08 15:12:08 +0200 |
| commit | 23a79730945f2a0e2cc61a2d6a37281dff4be81d (patch) | |
| tree | 2aaae75ae63fdc850c6a10053d42be4c0f58ff0b /passes/sat/example.ys | |
| parent | 92f04eab106ec10fe9b1d154e7e61dd017a2f145 (diff) | |
| download | yosys-23a79730945f2a0e2cc61a2d6a37281dff4be81d.tar.gz yosys-23a79730945f2a0e2cc61a2d6a37281dff4be81d.tar.bz2 yosys-23a79730945f2a0e2cc61a2d6a37281dff4be81d.zip | |
Added support for shifter cells to SAT generator
Diffstat (limited to 'passes/sat/example.ys')
| -rw-r--r-- | passes/sat/example.ys | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/example.ys b/passes/sat/example.ys index d4037f781..3de8c7997 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -2,4 +2,5 @@ read_verilog example.v proc; opt_clean sat_solve -set y 1'b1 example001 sat_solve -set y 1'b1 example002 -sat_solve -set y 1'b1 example003 +sat_solve -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 +sat_solve -set y 1'b1 example004 |