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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-09 09:46:37 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-09 09:46:37 +0200 |
commit | 7a860c562323b8279cdbb8626a47ac8466c78b4c (patch) | |
tree | d713b5c04ab34aadcbd310237a8cc46951f83e37 /passes/proc | |
parent | 8a3329871ba7bab98982a101327b8375cd73344d (diff) | |
parent | ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76 (diff) | |
download | yosys-7a860c562323b8279cdbb8626a47ac8466c78b4c.tar.gz yosys-7a860c562323b8279cdbb8626a47ac8466c78b4c.tar.bz2 yosys-7a860c562323b8279cdbb8626a47ac8466c78b4c.zip |
Merge remote-tracking branch 'upstream/master' into efinix
Diffstat (limited to 'passes/proc')
-rw-r--r-- | passes/proc/proc_prune.cc | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index 9e00b0a8a..b47ee79c2 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -82,14 +82,23 @@ struct PruneWorker if (root) { bool promotable = true; for (auto &bit : lhs) { - if (bit.wire && affected[bit]) { + if (bit.wire && affected[bit] && !assigned[bit]) { promotable = false; break; } } if (promotable) { + RTLIL::SigSpec rhs = sigmap(it->second); + RTLIL::SigSig conn; + for (int i = 0; i < GetSize(lhs); i++) { + RTLIL::SigBit lhs_bit = lhs[i]; + if (lhs_bit.wire && !assigned[lhs_bit]) { + conn.first.append_bit(lhs_bit); + conn.second.append(rhs.extract(i)); + } + } promoted_count++; - module->connect(*it); + module->connect(conn); remove.insert(*it); } } |