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| author | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
| commit | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch) | |
| tree | 4780799b6c1dc1d150b80aa142e6c53e06760cb3 /passes/proc | |
| parent | edff79a25a802e5b1816608b48e3ac335ad87147 (diff) | |
| parent | 694e30a35426b9582a1f2db730528d4d34305795 (diff) | |
| download | yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.gz yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.bz2 yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.zip | |
Merge branch 'master' into xc7dsp
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_clean.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 97f4c6573..114c6ab03 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -69,8 +69,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did did_something = true; for (auto &action : sw->cases[0]->actions) parent->actions.push_back(action); - for (auto sw2 : sw->cases[0]->switches) - parent->switches.push_back(sw2); + parent->switches.insert(parent->switches.begin(), sw->cases[0]->switches.begin(), sw->cases[0]->switches.end()); sw->cases[0]->switches.clear(); delete sw->cases[0]; sw->cases.clear(); |