diff options
| author | whitequark <whitequark@whitequark.org> | 2019-08-19 16:44:23 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-08-19 16:44:23 +0000 |
| commit | 4a942ba7b9bb76f207adf23369f46d31f7607b75 (patch) | |
| tree | 99aa7de39093fa08b8b531dc4454dede36bd72fb /passes/proc | |
| parent | 4adcbecec5c6bfcdd3ed1d6ed753d3a7670e3eea (diff) | |
| download | yosys-4a942ba7b9bb76f207adf23369f46d31f7607b75.tar.gz yosys-4a942ba7b9bb76f207adf23369f46d31f7607b75.tar.bz2 yosys-4a942ba7b9bb76f207adf23369f46d31f7607b75.zip | |
proc_clean: fix order of switch insertion.
Fixes #1268.
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_clean.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 97f4c6573..114c6ab03 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -69,8 +69,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did did_something = true; for (auto &action : sw->cases[0]->actions) parent->actions.push_back(action); - for (auto sw2 : sw->cases[0]->switches) - parent->switches.push_back(sw2); + parent->switches.insert(parent->switches.begin(), sw->cases[0]->switches.begin(), sw->cases[0]->switches.end()); sw->cases[0]->switches.clear(); delete sw->cases[0]; sw->cases.clear(); |