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| author | Jean-François Nguyen <jf@lambdaconcept.com> | 2019-07-31 14:26:09 +0200 |
|---|---|---|
| committer | Jean-François Nguyen <jf@lambdaconcept.com> | 2019-08-01 13:09:55 +0200 |
| commit | 320bf2fde55f72e7c0b35a0d9452e3777f13183d (patch) | |
| tree | dd5cc3ac8d543517aaba2182074009deca0a8619 /passes/proc | |
| parent | acd8bc0a7496c69864a7dd032eb7f4db7e2e1f2d (diff) | |
| download | yosys-320bf2fde55f72e7c0b35a0d9452e3777f13183d.tar.gz yosys-320bf2fde55f72e7c0b35a0d9452e3777f13183d.tar.bz2 yosys-320bf2fde55f72e7c0b35a0d9452e3777f13183d.zip | |
proc_prune: Promote partially redundant assignments.
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_prune.cc | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index 9e00b0a8a..b47ee79c2 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -82,14 +82,23 @@ struct PruneWorker if (root) { bool promotable = true; for (auto &bit : lhs) { - if (bit.wire && affected[bit]) { + if (bit.wire && affected[bit] && !assigned[bit]) { promotable = false; break; } } if (promotable) { + RTLIL::SigSpec rhs = sigmap(it->second); + RTLIL::SigSig conn; + for (int i = 0; i < GetSize(lhs); i++) { + RTLIL::SigBit lhs_bit = lhs[i]; + if (lhs_bit.wire && !assigned[lhs_bit]) { + conn.first.append_bit(lhs_bit); + conn.second.append(rhs.extract(i)); + } + } promoted_count++; - module->connect(*it); + module->connect(conn); remove.insert(*it); } } |