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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 21:56:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 21:56:45 -0700 |
| commit | 0391499e46cd69cf809fe911fa7798b1ae994540 (patch) | |
| tree | 32708f4d4386049a668e9eb4e88be5b4d53bed03 /passes/proc | |
| parent | fecafb2207efc772fec49b357bc6e20ca6a25aca (diff) | |
| parent | dca45c0888c44857038bd65b6f51f6d9f67b169f (diff) | |
| download | yosys-0391499e46cd69cf809fe911fa7798b1ae994540.tar.gz yosys-0391499e46cd69cf809fe911fa7798b1ae994540.tar.bz2 yosys-0391499e46cd69cf809fe911fa7798b1ae994540.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d2f8d9ead..7c334e661 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; + bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; |