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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
| commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/proc/proc_mux.cc | |
| parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
| download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip | |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/proc/proc_mux.cc')
| -rw-r--r-- | passes/proc/proc_mux.cc | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2ff755aef..30e7b748b 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -174,8 +174,15 @@ static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->get("\\S").append(ctrl_sig); - last_mux_cell->get("\\B").append(when_signal); + + RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); + new_s.append(ctrl_sig); + last_mux_cell->set("\\S", new_s); + + RTLIL::SigSpec new_b = last_mux_cell->get("\\B"); + new_b.append(when_signal); + last_mux_cell->set("\\B", new_b); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); } |