Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 15 insertions, 18 deletions

diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index fca20fda2..c72840c02 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -25,10 +25,9 @@
 
 static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
 {
-	assert(rule.compare.size() == 0);
+	log_assert(rule.compare.size() == 0);
 
 	while (1) {
-		sig.optimize();
 		RTLIL::SigSpec tmp = sig;
 		for (auto &it : rule.actions)
 			tmp.replace(it.first, it.second);
@@ -53,23 +52,21 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
 				RTLIL::SigSpec lhs = action.first;
 				RTLIL::SigSpec rhs = action.second;
 
-				lhs.optimize();
 				proc_get_const(rhs, proc->root_case);
 
 				if (!rhs.is_fully_const())
 					log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
 
 				int offset = 0;
-				for (size_t i = 0; i < lhs.chunks.size(); i++) {
-					if (lhs.chunks[i].wire == NULL)
-						continue;
-					RTLIL::Wire *wire = lhs.chunks[i].wire;
-					RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks[i].width);
-					if (value.width != wire->width)
-						log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks[i]), log_signal(value));
-					log("  Setting init value: %s = %s\n", log_signal(wire), log_signal(value));
-					wire->attributes["\\init"] = value.as_const();
-					offset += wire->width;
+				for (auto &lhs_c : lhs.chunks()) {
+					if (lhs_c.wire != NULL) {
+						RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
+						if (value.size() != lhs_c.wire->width)
+							log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
+						log("  Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
+						lhs_c.wire->attributes["\\init"] = value.as_const();
+					}
+					offset += lhs_c.width;
 				}
 			}
 		}
@@ -104,11 +101,11 @@ struct ProcInitPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
-			if (design->selected(mod_it.second))
-				for (auto &proc_it : mod_it.second->processes)
-					if (design->selected(mod_it.second, proc_it.second))
-						proc_init(mod_it.second, proc_it.second);
+		for (auto mod : design->modules())
+			if (design->selected(mod))
+				for (auto &proc_it : mod->processes)
+					if (design->selected(mod, proc_it.second))
+						proc_init(mod, proc_it.second);
 	}
 } ProcInitPass;