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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-31 15:45:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-31 15:45:15 -0700 |
| commit | e4a638c29297e3e8b915cf84a2dddc339f511476 (patch) | |
| tree | ed4a4b4153248291c6772db0c0c919679ecba7b8 /passes/pmgen | |
| parent | 84c7a562e597aaaacaab122a2ec7cbdf67ff6cfc (diff) | |
| download | yosys-e4a638c29297e3e8b915cf84a2dddc339f511476.tar.gz yosys-e4a638c29297e3e8b915cf84a2dddc339f511476.tar.bz2 yosys-e4a638c29297e3e8b915cf84a2dddc339f511476.zip | |
Restore old CO behaviour
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/ice40_dsp.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 369cb211e..00794ca0d 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -144,14 +144,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Output Interface SigSpec O = st.sigO; - if (GetSize(O) == 33) { - cell->setPort("\\CO", st.sigO[32]); - O.remove(32); + int O_width = GetSize(O); + if (O_width == 33) { + log_assert(st.addAB); + cell->setPort("\\CO", O[-1]); + O.remove(O_width-1); } - else { - log_assert(GetSize(O) <= 32); + else cell->setPort("\\CO", pm.module->addWire(NEW_ID)); - } + log_assert(GetSize(O) <= 32); if (GetSize(O) < 32) O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); |