diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 10:00:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 10:00:01 -0700 |
| commit | e3c39cc450a0317ad7e8234bb866d55465548c9c (patch) | |
| tree | 75f764e6a6ccf8c882b646bd83e2274e84099535 /passes/pmgen | |
| parent | d2c33863d08bbc506888b723a304aa11f8650296 (diff) | |
| download | yosys-e3c39cc450a0317ad7e8234bb866d55465548c9c.tar.gz yosys-e3c39cc450a0317ad7e8234bb866d55465548c9c.tar.bz2 yosys-e3c39cc450a0317ad7e8234bb866d55465548c9c.zip | |
Fix typo
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 4b566f0a6..73439cfd9 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -112,7 +112,7 @@ code addAB sigCD sigCD_signed sigO if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) reject; - if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) + if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool())) reject; sigO = port(addAB, \Y); |