diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 16:10:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 16:10:16 -0700 |
| commit | cd002ad3fb20bb98027f29e0c1005bf1df7c432c (patch) | |
| tree | d925c1c1185717f585f120408b2d8eb5a5343f08 /passes/pmgen/xilinx_dsp.cc | |
| parent | 2d80866dafe9e2e2edd2d49e999c1f6a35541852 (diff) | |
| download | yosys-cd002ad3fb20bb98027f29e0c1005bf1df7c432c.tar.gz yosys-cd002ad3fb20bb98027f29e0c1005bf1df7c432c.tar.bz2 yosys-cd002ad3fb20bb98027f29e0c1005bf1df7c432c.zip | |
Use choices for addAB, now called postAdd
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index b3d302071..7f51d29f6 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -39,7 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("ffB: %s\n", log_id(st.ffB, "--")); log("dsp: %s\n", log_id(st.dsp, "--")); log("ffM: %s\n", log_id(st.ffM, "--")); - log("addAB: %s\n", log_id(st.addAB, "--")); + log("postAdd: %s\n", log_id(st.postAdd, "--")); log("muxAB: %s\n", log_id(st.muxAB, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--")); @@ -53,10 +53,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) SigSpec C = st.sigC; SigSpec P = st.sigP; - if (st.addAB) { - log_assert(st.addAB->getParam("\\A_SIGNED").as_bool()); - log_assert(st.addAB->getParam("\\B_SIGNED").as_bool()); - log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); + if (st.postAdd) { + log_assert(st.postAdd->getParam("\\A_SIGNED").as_bool()); + log_assert(st.postAdd->getParam("\\B_SIGNED").as_bool()); + log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); SigSpec &opmode = cell->connections_.at("\\OPMODE"); if (st.ffP && st.muxAB) { @@ -72,7 +72,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) opmode[6] = State::S0; opmode[5] = State::S1; - pm.autoremove(st.addAB); + pm.autoremove(st.postAdd); } if (st.clock != SigBit()) |