diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 15:32:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 15:32:26 -0700 |
| commit | 74eac766995237dec86d51778811cf186c68d851 (patch) | |
| tree | cbe231b08944725d2181bc96c646f330ad31bf69 /passes/pmgen/xilinx_dsp.cc | |
| parent | ef56f8596fdd9753e93dbd654493497be8902691 (diff) | |
| download | yosys-74eac766995237dec86d51778811cf186c68d851.tar.gz yosys-74eac766995237dec86d51778811cf186c68d851.tar.bz2 yosys-74eac766995237dec86d51778811cf186c68d851.zip | |
Add support for DREG
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index d8213e02f..547073aa6 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -38,6 +38,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("ffAmux: %s\n", log_id(st.ffAmux, "--")); log("ffB: %s\n", log_id(st.ffB, "--")); log("ffBmux: %s\n", log_id(st.ffBmux, "--")); + log("ffD: %s\n", log_id(st.ffD, "--")); + log("ffDmux: %s\n", log_id(st.ffDmux, "--")); log("dsp: %s\n", log_id(st.dsp, "--")); log("ffM: %s\n", log_id(st.ffM, "--")); log("ffMmux: %s\n", log_id(st.ffMmux, "--")); @@ -141,6 +143,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) cell->setParam("\\BREG", 1); } + if (st.ffD) { + if (st.ffDmux) { + SigSpec S = st.ffDmux->getPort("\\S"); + cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S)); + } + else + cell->setPort("\\CED", State::S1); + cell->setPort("\\D", st.sigD); + + cell->setParam("\\DREG", 1); + } if (st.ffM) { if (st.ffMmux) { SigSpec S = st.ffMmux->getPort("\\S"); |