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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 17:06:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 17:06:17 -0700 |
| commit | 42548d979018c4bc3b71d4faa0900b18d2d290ec (patch) | |
| tree | 6c0a9a0f1c5d5d3fce3ad9d28e6391ec68c73399 /passes/pmgen/xilinx_dsp.cc | |
| parent | 93d798272d027f15aa930766bc3f9553f448f5cf (diff) | |
| download | yosys-42548d979018c4bc3b71d4faa0900b18d2d290ec.tar.gz yosys-42548d979018c4bc3b71d4faa0900b18d2d290ec.tar.bz2 yosys-42548d979018c4bc3b71d4faa0900b18d2d290ec.zip | |
Get rid of sigPused
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 4d2152f61..0d1937844 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -43,8 +43,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("postAdd: %s\n", log_id(st.postAdd, "--")); log("postAddMux: %s\n", log_id(st.postAddMux, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); - //log("muxP: %s\n", log_id(st.muxP, "--")); - log("sigPused: %s\n", log_signal(st.sigPused)); #endif log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp)); |