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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:00:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:00:56 -0700 |
| commit | 390cf34d0a8f815ea9828f9a455b36164f9d5607 (patch) | |
| tree | d20e4091197cdf45bfeb52be7b38468350f06e36 /passes/pmgen/xilinx_dsp.cc | |
| parent | 2983a35dc058a5f5a1ab7b23cc55dd6f83667d88 (diff) | |
| download | yosys-390cf34d0a8f815ea9828f9a455b36164f9d5607.tar.gz yosys-390cf34d0a8f815ea9828f9a455b36164f9d5607.tar.bz2 yosys-390cf34d0a8f815ea9828f9a455b36164f9d5607.zip | |
Add support for ffM
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index e7b72e312..105ad1fa1 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -39,6 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("ffB: %s\n", log_id(st.ffB, "--")); log("dsp: %s\n", log_id(st.dsp, "--")); log("addAB: %s\n", log_id(st.addAB, "--")); + log("ffM: %s\n", log_id(st.ffM, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--")); log("sigPused: %s\n", log_signal(st.sigPused)); @@ -95,6 +96,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) // cell->setPort("\\CEB2", st.ffB->getPort("\\EN")); else log_abort(); } + if (st.ffM) { + SigSpec D = st.ffM->getPort("\\D"); + SigSpec Q = st.ffM->getPort("\\Q"); + P.replace(pm.sigmap(D), Q); + cell->setParam("\\MREG", State::S1); + if (st.ffP->type == "$dff") + cell->setPort("\\CEM", State::S1); + //else if (st.ffP->type == "$dffe") + // cell->setPort("\\CEP", st.ffP->getPort("\\EN")); + else log_abort(); + } if (st.ffP) { SigSpec D; //if (st.muxP) |