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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 14:10:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 14:10:12 -0700 |
| commit | 2c32056990b9742839841f4cf3fa31d742cef472 (patch) | |
| tree | ede6d224e36e822ab468e42b46056f7c496ffd7c /passes/pmgen/xilinx_dsp.cc | |
| parent | e926f2973e5c6bf8e00cd67fc44200ceb47e215e (diff) | |
| download | yosys-2c32056990b9742839841f4cf3fa31d742cef472.tar.gz yosys-2c32056990b9742839841f4cf3fa31d742cef472.tar.bz2 yosys-2c32056990b9742839841f4cf3fa31d742cef472.zip | |
Logging for ffAD
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 9587ed28a..65a4d5a11 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -177,6 +177,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) if (st.ffA) log(" ffA:%s", log_id(st.ffA)); + if (st.ffAD) + log(" ffAD:%s", log_id(st.ffAD)); + if (st.ffB) log(" ffB:%s", log_id(st.ffB)); |