diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-22 15:05:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-22 15:05:16 -0700 |
| commit | 304cefbbe2b0c000c30e8d73d1761488be65ccf0 (patch) | |
| tree | 47364841aeb8dd908f9d3de9e8bfcc7abb2309a1 /passes/pmgen/ice40_dsp.pmg | |
| parent | 5e70b8a22bf38e622943b0546255befd539fa884 (diff) | |
| download | yosys-304cefbbe2b0c000c30e8d73d1761488be65ccf0.tar.gz yosys-304cefbbe2b0c000c30e8d73d1761488be65ccf0.tar.bz2 yosys-304cefbbe2b0c000c30e8d73d1761488be65ccf0.zip | |
Pack Y register
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index a92cf8dd4..223f9b2e4 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -143,17 +143,21 @@ endcode match ffS if muxAB select ffS->type.in($dff) - select nusers(port(ffS, \D)) == 2 - index <SigSpec> port(ffS, \D) === port(muxAB, \Y) - index <SigSpec> port(ffS, \Q) === sigS + filter nusers(port(muxAB, \Y)) == 2 + filter includes(port(ffS, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set()) optional endmatch -code clock clock_pol +code clock clock_pol sigS if (ffS) { SigBit c = port(ffS, \CLK).as_bit(); bool cp = param(ffS, \CLK_POLARITY).as_bool(); + if (port(ffS, \Q) != sigS) { + sigS = port(muxAB, \Y); + sigS.replace(port(ffS, \D), port(ffS, \Q)); + } + if (clock != SigBit() && (c != clock || cp != clock_pol)) reject; |