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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 15:13:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 15:13:30 -0700 |
| commit | 79fd6edc5a076d263a9d68f0e1a103a9d643a9df (patch) | |
| tree | 42a1411ea8e8b3747b63ee7fa390abe227b5d623 /passes/pmgen/ice40_dsp.cc | |
| parent | 151c5c96c0a85a1b69fc7824949ed89d70667059 (diff) | |
| download | yosys-79fd6edc5a076d263a9d68f0e1a103a9d643a9df.tar.gz yosys-79fd6edc5a076d263a9d68f0e1a103a9d643a9df.tar.bz2 yosys-79fd6edc5a076d263a9d68f0e1a103a9d643a9df.zip | |
Eliminate warnings by sizing O correctly
Diffstat (limited to 'passes/pmgen/ice40_dsp.cc')
| -rw-r--r-- | passes/pmgen/ice40_dsp.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index ee4e4f5e8..3ceffdbf6 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -144,7 +144,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Output Interface - cell->setPort("\\O", st.sigO); + SigSpec O = st.sigO; + if (GetSize(O) < 32) + O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); + + cell->setPort("\\O", O); bool accum = false; if (st.addAB) { |