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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
| commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
| tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/opt | |
| parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
| download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip | |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 | ||||
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 0be36606d..ba0aadc6b 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -241,8 +241,6 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { - new_conn.first.optimize(); - new_conn.second.optimize(); used_signals.add(new_conn.first); used_signals.add(new_conn.second); module->connections.push_back(new_conn); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ff139854f..800fbf109 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -481,8 +481,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { - new_a.optimize(); - new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; cell->parameters["\\A_WIDTH"] = new_a.size(); |