diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-03-08 09:16:25 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-08 09:16:25 +0100 |
| commit | b96ffed69b1445cadb4eee0cc5272dd8b1bc915e (patch) | |
| tree | be09e71918699b1157c3e0063b6ae3fa0c8658ca /passes/opt | |
| parent | 79b3afa0110f975f300674426c938bab25d76baf (diff) | |
| download | yosys-b96ffed69b1445cadb4eee0cc5272dd8b1bc915e.tar.gz yosys-b96ffed69b1445cadb4eee0cc5272dd8b1bc915e.tar.bz2 yosys-b96ffed69b1445cadb4eee0cc5272dd8b1bc915e.zip | |
Automatically select new objects in abc and techmap passes
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_rmunused.cc | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc index 4807a97b6..3276ad626 100644 --- a/passes/opt/opt_rmunused.cc +++ b/passes/opt/opt_rmunused.cc @@ -118,6 +118,17 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2) return w2->name < w1->name; } +static bool check_public_name(RTLIL::IdString id) +{ + if (id[0] == '$') + return false; +#if 0 + if (id.find(".$") == std::string::npos) + return true; +#endif + return false; +} + static void rmunused_module_signals(RTLIL::Module *module) { SigMap assign_map(module); @@ -157,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module) std::vector<RTLIL::Wire*> del_wires; for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; - if (wire->name[0] == '\\') { + if (check_public_name(wire->name)) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; assign_map.apply(s2); if (!used_signals.check_any(s2) && wire->port_id == 0) { |