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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-06 14:18:34 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-06 14:18:34 +0100 |
| commit | 9b9c3327ccf3a8e69f9af57333839f470df0ce66 (patch) | |
| tree | 8871c90547605199fc115e20c19a3a3614695823 /passes/opt | |
| parent | 973507d85b0a20118f6a56ec787d44d6b574d3a6 (diff) | |
| download | yosys-9b9c3327ccf3a8e69f9af57333839f470df0ce66.tar.gz yosys-9b9c3327ccf3a8e69f9af57333839f470df0ce66.tar.bz2 yosys-9b9c3327ccf3a8e69f9af57333839f470df0ce66.zip | |
Fixed undef handling in opt_reduce
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_reduce.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index dd1299810..fee8fb71b 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -65,8 +65,8 @@ struct OptReduceWorker continue; } if (chunk.wire == NULL) { - new_sig_a = RTLIL::SigSpec(RTLIL::State::Sx); - break; + new_sig_a.append(chunk); + continue; } bool imported_children = false; |