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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-10 20:51:37 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-10 20:51:37 +0100 |
| commit | 87819c62fae8846339077da2cf7080a765cd14f9 (patch) | |
| tree | 5e30a45883a3bd678a6831c9e42e9ad31e50137a /passes/opt | |
| parent | 4f68a77e3f03aac0dc18caeb02b19b100f04879d (diff) | |
| download | yosys-87819c62fae8846339077da2cf7080a765cd14f9.tar.gz yosys-87819c62fae8846339077da2cf7080a765cd14f9.tar.bz2 yosys-87819c62fae8846339077da2cf7080a765cd14f9.zip | |
Less aggressive "share" defaults
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/share.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 3133cb2a6..9cd0ccc03 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -369,7 +369,9 @@ struct ShareWorker } if (cell->type == "$memrd") { - if (!cell->parameters.at("\\CLK_ENABLE").as_bool()) + if (cell->parameters.at("\\CLK_ENABLE").as_bool()) + continue; + if (config.opt_aggressive || !modwalker.sigmap(cell->getPort("\\ADDR")).is_fully_const()) shareable_cells.insert(cell); continue; } @@ -387,7 +389,7 @@ struct ShareWorker } if (generic_ops.count(cell->type)) { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10) + if (config.opt_aggressive) shareable_cells.insert(cell); continue; } @@ -1105,7 +1107,7 @@ struct ShareWorker RTLIL::Cell *cell = *shareable_cells.begin(); shareable_cells.erase(cell); - log(" Analyzing resource sharing options for %s:\n", log_id(cell)); + log(" Analyzing resource sharing options for %s (%s):\n", log_id(cell), log_id(cell->type)); const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, " "); RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); @@ -1138,7 +1140,7 @@ struct ShareWorker for (auto other_cell : candidates) { - log(" Analyzing resource sharing with %s:\n", log_id(other_cell)); + log(" Analyzing resource sharing with %s (%s):\n", log_id(other_cell), log_id(other_cell->type)); const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " "); RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); |