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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-11 16:59:10 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 16:20:56 +0200 |
| commit | 85166633bc981b02e31167134917fc0b523e8eda (patch) | |
| tree | d0660300d51941222baf2b2cf3b7edff00ef39f6 /passes/opt | |
| parent | 2d436bc4f1f3ca574a89312caf0bf94b81b37f7a (diff) | |
| download | yosys-85166633bc981b02e31167134917fc0b523e8eda.tar.gz yosys-85166633bc981b02e31167134917fc0b523e8eda.tar.bz2 yosys-85166633bc981b02e31167134917fc0b523e8eda.zip | |
opt_clean: Add missing assignments to opt.did_something.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index da3961218..6271376f1 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -406,6 +406,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (verbose && del_temp_wires_count) log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count); + if (!del_wires_queue.empty()) + module->design->scratchpad_set_bool("opt.did_something", true); + return !del_wires_queue.empty(); } @@ -476,6 +479,9 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) next_wire:; } + if (did_something) + module->design->scratchpad_set_bool("opt.did_something", true); + return did_something; } |