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| author | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-14 11:39:24 +0200 |
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| committer | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-14 11:39:24 +0200 |
| commit | 53695e6729e8ae603be7e7cd9bc8b29758d61a11 (patch) | |
| tree | 3fa7d76ed7e4aa7b4d560cf4020f391ef733639c /passes/opt | |
| parent | 291b36afeb1075b7c6329d1e57594ed3e6b71581 (diff) | |
| download | yosys-53695e6729e8ae603be7e7cd9bc8b29758d61a11.tar.gz yosys-53695e6729e8ae603be7e7cd9bc8b29758d61a11.tar.bz2 yosys-53695e6729e8ae603be7e7cd9bc8b29758d61a11.zip | |
Prepare for situation when port of the signal cannot be found
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 41bbdcd57..cf89ac096 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -503,7 +503,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) // If the register bit cannot change, we can replace it with a constant if (!counter_example_found) { - RTLIL::SigBit &driver_port = net.driver_port(q_sigbit); + RTLIL::SigSpec driver_port = net.driver_port(q_sigbit); RTLIL::Wire *dummy_wire = mod->addWire(NEW_ID, 1); for (auto &conn : mod->connections_) |