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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-24 00:13:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-24 00:13:27 +0100 |
| commit | 43951099cf46b5a0a25bdebb001685a89dfe6c82 (patch) | |
| tree | b95a7ef79401216e1e65b30691b4ecaa2e7491af /passes/opt | |
| parent | 1cb4c925d03de289f37a40b6eceb57ced8dce295 (diff) | |
| download | yosys-43951099cf46b5a0a25bdebb001685a89dfe6c82.tar.gz yosys-43951099cf46b5a0a25bdebb001685a89dfe6c82.tar.bz2 yosys-43951099cf46b5a0a25bdebb001685a89dfe6c82.zip | |
Added dict/pool.sort()
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index c5b25816c..98f83dffc 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -422,6 +422,10 @@ struct CleanPass : public Pass { if (count_rm_cells > 0 || count_rm_wires > 0) log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires); + design->optimize(); + design->sort(); + design->check(); + ct.clear(); ct_reg.clear(); ct_all.clear(); |