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| author | Clifford Wolf <clifford@clifford.at> | 2013-05-17 14:55:18 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-05-17 14:55:18 +0200 |
| commit | 3ecc31423811c87e3511c62db4f86760e4a634b0 (patch) | |
| tree | 4c7bb9cc6aa07de13136a45221dd0a9a4d12b264 /passes/opt | |
| parent | 59d0c75b9877fc8413b863060b2172b004354c3a (diff) | |
| download | yosys-3ecc31423811c87e3511c62db4f86760e4a634b0.tar.gz yosys-3ecc31423811c87e3511c62db4f86760e4a634b0.tar.bz2 yosys-3ecc31423811c87e3511c62db4f86760e4a634b0.zip | |
Fixed to aggressive x-folding in opt_const
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_const.cc | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7c82f0fcb..149bd97d5 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -28,7 +28,7 @@ #include <stdio.h> #include <set> -bool did_something; +static bool did_something; void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { @@ -44,7 +44,7 @@ void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, st did_something = true; } -void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) +void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x) { if (!design->selected(module)) return; @@ -78,8 +78,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match(" 0")) ACTION_DO_Y(0); if (input.match("0 ")) ACTION_DO_Y(0); if (input.match("11")) ACTION_DO_Y(1); - if (input.match(" *")) ACTION_DO_Y(x); - if (input.match("* ")) ACTION_DO_Y(x); + if (input.match("**")) ACTION_DO_Y(x); + if (input.match("1*")) ACTION_DO_Y(x); + if (input.match("*1")) ACTION_DO_Y(x); + if (consume_x) { + if (input.match(" *")) ACTION_DO_Y(0); + if (input.match("* ")) ACTION_DO_Y(0); + } if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1)); if (input.match("1 ")) ACTION_DO("\\Y", input.extract(0, 1)); } @@ -92,8 +97,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match(" 1")) ACTION_DO_Y(1); if (input.match("1 ")) ACTION_DO_Y(1); if (input.match("00")) ACTION_DO_Y(0); - if (input.match(" *")) ACTION_DO_Y(x); - if (input.match("* ")) ACTION_DO_Y(x); + if (input.match("**")) ACTION_DO_Y(x); + if (input.match("0*")) ACTION_DO_Y(x); + if (input.match("*0")) ACTION_DO_Y(x); + if (consume_x) { + if (input.match(" *")) ACTION_DO_Y(1); + if (input.match("* ")) ACTION_DO_Y(1); + } if (input.match(" 0")) ACTION_DO("\\Y", input.extract(1, 1)); if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1)); } @@ -308,8 +318,11 @@ struct OptConstPass : public Pass { for (auto &mod_it : design->modules) do { - did_something = false; - replace_const_cells(design, mod_it.second); + do { + did_something = false; + replace_const_cells(design, mod_it.second, false); + } while (did_something); + replace_const_cells(design, mod_it.second, true); } while (did_something); log_pop(); |