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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-15 16:01:00 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-15 16:01:00 +0200 |
| commit | 287de4b848bdd33a9ba52018fc9b9779a10e60c7 (patch) | |
| tree | 3b98729d46c1c4c3647ea5d1d1812659a18bcf9b /passes/opt | |
| parent | f67ec1b2350c3bd88edacba7ad799bf60b33da61 (diff) | |
| download | yosys-287de4b848bdd33a9ba52018fc9b9779a10e60c7.tar.gz yosys-287de4b848bdd33a9ba52018fc9b9779a10e60c7.tar.bz2 yosys-287de4b848bdd33a9ba52018fc9b9779a10e60c7.zip | |
Add rewrite_sigspecs2, Improve remove() wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/opt')
0 files changed, 0 insertions, 0 deletions