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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 14:40:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 14:40:57 -0700 |
| commit | 09beeee38a5af767f70d24e86c976e43b1b27547 (patch) | |
| tree | c5655a7c18ef02dc8a90e8c166511d6d85851444 /passes/opt | |
| parent | c926eeb43a9c42a0ecc34871f383f4181b7a45f9 (diff) | |
| download | yosys-09beeee38a5af767f70d24e86c976e43b1b27547.tar.gz yosys-09beeee38a5af767f70d24e86c976e43b1b27547.tar.bz2 yosys-09beeee38a5af767f70d24e86c976e43b1b27547.zip | |
Try and fix again
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/wreduce.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 908a85d5b..22af0bd8b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -372,13 +372,12 @@ struct WreduceWorker int i; for (i = 0; i < GetSize(sig); i++) { - if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0)) - break; - if (B[i] == S0) + if (B.at(i, Sx) == S0 && A.at(i, Sx) != Sx) module->connect(sig[i], A[i]); - else if (A[i] == S0) + else if (!sub && A.at(i, Sx) == S0 && B.at(i, Sx) != Sx) module->connect(sig[i], B[i]); - else log_abort(); + else + break; } if (i > 0) { cell->setPort("\\A", A.extract(i, -1)); |