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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 13:16:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 13:16:03 -0800 |
| commit | f7c7003a193361285ba59d1315c1e7c26c4c52f1 (patch) | |
| tree | 1b5ef37eb342883aec8b3b306cd410a660311d21 /passes/opt/wreduce.cc | |
| parent | dfb23a79dd0e2ffbe4f058eadb552d8194540eef (diff) | |
| parent | 7a40294e93490fa462343244b1e2881c3c249c3f (diff) | |
| download | yosys-f7c7003a193361285ba59d1315c1e7c26c4c52f1.tar.gz yosys-f7c7003a193361285ba59d1315c1e7c26c4c52f1.tar.bz2 yosys-f7c7003a193361285ba59d1315c1e7c26c4c52f1.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/opt/wreduce.cc')
| -rw-r--r-- | passes/opt/wreduce.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 3aa916ec2..09983bc67 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -195,6 +195,13 @@ struct WreduceWorker for (auto bit : sig_q) work_queue_bits.insert(bit); + // Narrow ARST_VALUE parameter to new size. + if (cell->parameters.count("\\ARST_VALUE")) { + Const arst_value = cell->getParam("\\ARST_VALUE"); + arst_value.bits.resize(GetSize(sig_q)); + cell->setParam("\\ARST_VALUE", arst_value); + } + cell->setPort("\\D", sig_d); cell->setPort("\\Q", sig_q); cell->fixup_parameters(); |