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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:25:50 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:25:50 -0700 |
commit | bfc7164af7bf64cb2fe5d00e87bbfead841a4dc2 (patch) | |
tree | 0a0465a967768c06db0f2f2ca401c612d1d3d53f /passes/opt/wreduce.cc | |
parent | 84f52aee0d01378796792c9a2f068a22d955f586 (diff) | |
download | yosys-bfc7164af7bf64cb2fe5d00e87bbfead841a4dc2.tar.gz yosys-bfc7164af7bf64cb2fe5d00e87bbfead841a4dc2.tar.bz2 yosys-bfc7164af7bf64cb2fe5d00e87bbfead841a4dc2.zip |
Move LSB-trimming functionality from wreduce to opt_expr
Diffstat (limited to 'passes/opt/wreduce.cc')
-rw-r--r-- | passes/opt/wreduce.cc | 24 |
1 files changed, 1 insertions, 23 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 22af0bd8b..1eeca2748 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -365,28 +365,6 @@ struct WreduceWorker } } - if (cell->type.in("$add", "$sub")) { - SigSpec A = mi.sigmap(cell->getPort("\\A")); - SigSpec B = mi.sigmap(cell->getPort("\\B")); - bool sub = cell->type == "$sub"; - - int i; - for (i = 0; i < GetSize(sig); i++) { - if (B.at(i, Sx) == S0 && A.at(i, Sx) != Sx) - module->connect(sig[i], A[i]); - else if (!sub && A.at(i, Sx) == S0 && B.at(i, Sx) != Sx) - module->connect(sig[i], B[i]); - else - break; - } - if (i > 0) { - cell->setPort("\\A", A.extract(i, -1)); - cell->setPort("\\B", B.extract(i, -1)); - sig.remove(0, i); - bits_removed += i; - } - } - if (GetSize(sig) == 0) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->remove(cell); @@ -394,7 +372,7 @@ struct WreduceWorker } if (bits_removed) { - log("Removed %d bits (of %d) from port Y of cell %s.%s (%s).\n", + log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort("\\Y", sig); did_something = true; |