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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-15 14:57:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-15 14:57:28 +0200 |
| commit | 1d83854d84b7a0a23ee14b72c1a289b50becdeca (patch) | |
| tree | 443eb4c608d49541e461fd45f825bf93a36aea71 /passes/opt/wreduce.cc | |
| parent | 5dd3e93e8f23015d23915ee88f6ffec56166494a (diff) | |
| download | yosys-1d83854d84b7a0a23ee14b72c1a289b50becdeca.tar.gz yosys-1d83854d84b7a0a23ee14b72c1a289b50becdeca.tar.bz2 yosys-1d83854d84b7a0a23ee14b72c1a289b50becdeca.zip | |
Bugfixes in handling of "keep" attribute on wires
Diffstat (limited to 'passes/opt/wreduce.cc')
| -rw-r--r-- | passes/opt/wreduce.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index e551443ff..c194d428d 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -51,6 +51,7 @@ struct WreduceWorker std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells; std::set<SigBit> work_queue_bits; + pool<SigBit> keep_bits; WreduceWorker(WreduceConfig *config, Module *module) : config(config), module(module), mi(module) { } @@ -68,7 +69,7 @@ struct WreduceWorker for (int i = GetSize(sig_y)-1; i >= 0; i--) { auto info = mi.query(sig_y[i]); - if (!info->is_output && GetSize(info->ports) <= 1) { + if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) { bits_removed.push_back(Sx); continue; } @@ -265,6 +266,11 @@ struct WreduceWorker void run() { + for (auto w : module->wires()) + if (w->get_bool_attribute("\\keep")) + for (auto bit : mi.sigmap(w)) + keep_bits.insert(bit); + for (auto c : module->selected_cells()) work_queue_cells.insert(c); |