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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /passes/opt/opt_rmdff.cc | |
parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'passes/opt/opt_rmdff.cc')
-rw-r--r-- | passes/opt/opt_rmdff.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 5880254c1..e8570f0eb 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } else { @@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } + + return true; } - else + + if (!hasreset) { IdString new_type; @@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetPort("\\S"); cell->unsetPort("\\R"); - return did_something; + return true; } + + return did_something; } bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) |