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authorJim Lawson <ucbjrl@berkeley.edu>2019-04-30 13:19:27 -0700
committerJim Lawson <ucbjrl@berkeley.edu>2019-04-30 13:19:27 -0700
commit58650ffe876d1caedd8ffc9b0207f5cf75eef97b (patch)
tree5389584f1c3ad8c9e9003e78d4b6e22dca5e3a83 /passes/opt/opt_merge.cc
parent354ba5ba83f7b1fc3bb07aa6bf26dde7a00201d1 (diff)
parente35fe1344dd4c8f11632ed2a7f5b0463352a1ee4 (diff)
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Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'passes/opt/opt_merge.cc')
-rw-r--r--passes/opt/opt_merge.cc8
1 files changed, 5 insertions, 3 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index eedf88904..7567d4657 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -315,17 +315,17 @@ struct OptMergeWorker
{
if (sharemap.count(cell) > 0) {
did_something = true;
- log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
+ log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
for (auto &it : cell->connections()) {
if (cell->output(it.first)) {
RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
- log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
+ log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_signal(it.second), log_signal(other_sig));
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
}
}
- log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+ log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
#ifdef USE_CELL_HASH_CACHE
cell_hash_cache.erase(cell);
#endif
@@ -336,6 +336,8 @@ struct OptMergeWorker
}
}
}
+
+ log_suppressed();
}
};