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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 20:27:51 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-23 14:30:56 +0200 |
| commit | a23d9409e7d04fcfa31a139d0cf6169be4c46fca (patch) | |
| tree | 9ae67eb7826799ab60fabdcaf44c93e660f69996 /passes/opt/opt_mem.cc | |
| parent | 039f4f48d55609f254850112a948f26e66550095 (diff) | |
| download | yosys-a23d9409e7d04fcfa31a139d0cf6169be4c46fca.tar.gz yosys-a23d9409e7d04fcfa31a139d0cf6169be4c46fca.tar.bz2 yosys-a23d9409e7d04fcfa31a139d0cf6169be4c46fca.zip | |
opt_mem: Remove write ports with const-0 EN.
Fixes #2765.
Diffstat (limited to 'passes/opt/opt_mem.cc')
| -rw-r--r-- | passes/opt/opt_mem.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index 49a0ac51a..0409fb736 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -52,6 +52,18 @@ struct OptMemPass : public Pass { int total_count = 0; for (auto module : design->selected_modules()) { for (auto &mem : Mem::get_selected_memories(module)) { + bool changed = false; + for (auto &port : mem.wr_ports) { + if (port.en.is_fully_zero()) { + port.removed = true; + changed = true; + total_count++; + } + } + if (changed) { + mem.emit(); + } + if (mem.wr_ports.empty() && mem.inits.empty()) { mem.remove(); total_count++; |