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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 20:54:29 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-11 13:34:10 +0200 |
| commit | fd7921776387a05edadcc90d1300670d49a73d68 (patch) | |
| tree | 84fb8ab2ff4c012b5dd24e8c3dcd5dace93474fb /passes/opt/opt_expr.cc | |
| parent | b96eb888cc7518c20532ff688ec24b8b51f88f8e (diff) | |
| download | yosys-fd7921776387a05edadcc90d1300670d49a73d68.tar.gz yosys-fd7921776387a05edadcc90d1300670d49a73d68.tar.bz2 yosys-fd7921776387a05edadcc90d1300670d49a73d68.zip | |
Add v2 memory cells.
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index b7bbb2adf..cdd821c52 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -441,7 +441,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!noclkinv) { - if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr))) + if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2))) handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map); if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) { |