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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 10:51:34 +0200 |
| commit | 69fb3b8db21c8a50fa333bff3ef844af42729e0d (patch) | |
| tree | 1a62aebe9ece22b19b4087f2c5cb5581b571c270 /passes/opt/opt_expr.cc | |
| parent | 72323e11a4ee222c0ce928669d33333c46fb25aa (diff) | |
| parent | fa989e59e5a37d804d8a82050e022b8f4b7070d8 (diff) | |
| download | yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.gz yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.tar.bz2 yosys-69fb3b8db21c8a50fa333bff3ef844af42729e0d.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 00d7d6063..6cf66fb95 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (b.is_fully_const()) { + if (b.is_fully_undef()) { + RTLIL::SigSpec input = b; + ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y)))); + } else if (b.as_bool() == (cell->type == ID($eq))) { RTLIL::SigSpec input = b; ACTION_DO(ID::Y, cell->getPort(ID::A)); |