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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
| commit | edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 (patch) | |
| tree | 602fc633af5de89d2d6d1bda480159318f4aa91d /passes/opt/opt_const.cc | |
| parent | 48ca1ff9ef5bba939348ceeec75ad310afd9fcf8 (diff) | |
| download | yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.gz yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.bz2 yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.zip | |
Renamed extend() to extend_xx(), changed most users to extend_u0()
Diffstat (limited to 'passes/opt/opt_const.cc')
| -rw-r--r-- | passes/opt/opt_const.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 1e59f18c1..5bac76cf6 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -491,7 +491,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); - new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); + new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y); goto next_cell; } @@ -504,7 +504,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (new_a.size() == 0) { cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); - new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); + new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "empty", "\\Y", new_y); goto next_cell; } @@ -560,7 +560,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int()); if (GetSize(sig_a) < GetSize(sig_y)) - sig_a.extend(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); + sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); for (int i = 0; i < GetSize(sig_y); i++) { int idx = i + shift_bits; |