diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 16:09:27 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 19:34:51 +0200 |
commit | a62c21c9c64ad5b3e0dae5d4ee4857425f73068e (patch) | |
tree | 81cbbd4bbd869af6290eb0e19e4cfdfbc9555c03 /passes/opt/opt_const.cc | |
parent | 54552f680938fd933b07fa38597937ba6d367be7 (diff) | |
download | yosys-a62c21c9c64ad5b3e0dae5d4ee4857425f73068e.tar.gz yosys-a62c21c9c64ad5b3e0dae5d4ee4857425f73068e.tar.bz2 yosys-a62c21c9c64ad5b3e0dae5d4ee4857425f73068e.zip |
Removed RTLIL::SigSpec::expand() method
Diffstat (limited to 'passes/opt/opt_const.cc')
-rw-r--r-- | passes/opt/opt_const.cc | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 9b89291b1..ff139854f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -458,21 +458,19 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } RTLIL::SigSpec new_a, new_b; - a.expand(), b.expand(); - assert(a.chunks().size() == b.chunks().size()); - for (size_t i = 0; i < a.chunks().size(); i++) { - if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] && - a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) { + assert(SIZE(a) == SIZE(b)); + for (int i = 0; i < SIZE(a); i++) { + if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (a.chunks()[i] == b.chunks()[i]) + if (a[i] == b[i]) continue; - new_a.append(a.chunks()[i]); - new_b.append(b.chunks()[i]); + new_a.append(a[i]); + new_b.append(b[i]); } if (new_a.size() == 0) { |