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author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 15:05:18 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 17:56:19 +0200 |
commit | 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 (patch) | |
tree | 991a75afe9b009486a57834fefee075ec695a28c /passes/opt/opt_const.cc | |
parent | 5826670009e1018734de49aaf1554cb8a43d09d7 (diff) | |
download | yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.gz yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.tar.bz2 yosys-2bec47a4045d23d46e7d300cbf80b2dce1a549a9.zip |
Use only module->addCell() and module->remove() to create and delete cells
Diffstat (limited to 'passes/opt/opt_const.cc')
-rw-r--r-- | passes/opt/opt_const.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index e2bf7004f..e1b6c598f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -81,8 +81,7 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i module->name.c_str(), log_signal(Y), log_signal(out_val)); // ILANG_BACKEND::dump_cell(stderr, "--> ", cell); module->connections.push_back(RTLIL::SigSig(Y, out_val)); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); OPT_DID_SOMETHING = true; did_something = true; } |